1. Technical Field
The present disclosure relates to semiconductor memory devices, and more particularly, to a semiconductor memory device that can adjust the voltage level of a column selection line.
2. Discussion of Related Art
A semiconductor memory device has memory cells connected between word lines and bit lines. When a semiconductor memory device receives addresses from the outside during a read operation, a row decoder decodes a row address among the addresses and activates the corresponding word line. Memory cells connected with the activated word line apply stored data to bit-line pairs, and sense amplifiers sense and amplify the data applied through the corresponding bit-line pairs. A column decoder activated in response to a column enable signal decodes a column address among the addresses and activates a predetermined number of column selection lines to a predetermined voltage level. The activated column selection lines activate input/output (I/O) gates for connecting bit-line pairs with the corresponding I/O line pairs. When the bit-line pairs are connected with the I/O line pairs by the activated I/O gates, the amplified data on the bit-line pairs is output to the outside through the I/O lines.
A point in time at which the column enable signal is activated is determined by row address strobe (RAS) to column address strobe (CAS) delay time (tRCD) that indicates a delay until a read command or write command is input after an active command is input. The column enable signal is set to be activated after data of a memory cell is carried on a bit-line pair and a minute voltage difference between the bit-line pair is completely amplified by a sense amplifier. During a read operation of the semiconductor memory device, the column enable signal may be activated with the voltage difference between the bit-line pair not completely amplified, and a column selection line activated by the column decoder may turn on an I/O gate. In this case, the voltage level of the bit-line pair may be distorted by the voltage of an I/O line pair driven to a higher voltage level than the bit-line pair.
On the other hand, when a bit-line pair is connected with an I/O line pair by an activated I/O gate during a write operation of the semiconductor memory device, data of the bit-line pair is converted into data applied through an I/O line pair. Then, data of the bit-line pair is amplified by a sense amplifier and stored in a memory cell connected with an activated word line.
Currently, a column selection line is generally driven for activation to an external power supply voltage level which is higher than an internal supply voltage level regardless of a read or write operation of a semiconductor memory device in order to rapidly convert data of a bit-line pair into data of an I/O line pair during the write operation. When a semiconductor memory device drives a column selection line to an external power supply voltage level, a sudden change in the voltage level of a bit-line pair may be caused by a voltage precharged to an I/O line pair during a read operation, and the read operation may be slowed down. Otherwise, the voltage levels of a bit line and an inverted bit line may be reversely sensed and amplified, and data of the bit-line pair may be switched.